An input circuit in a semiconductor integrated circuit device generally identifies two states, i.e., high and low levels of an external signal. There is also an input circuit designed to be capable of identifying three states, i.e., high, intermediate and low levels of an external signal in order to reduce the terminals of the semiconductor device for reducing the package costs (for example, Japanese Patent Laying-Open No. 6-104664 (Patent Document 1)).
FIG. 3 is a circuit diagram showing a schematic configuration of an input circuit of Japanese Patent Laying-Open No. 6-104664 (Patent Document 1). Referring to the drawing, an input circuit 101 includes a comparator 103, a comparator 104 and a combinational circuit 105.
Comparator 103 and comparator 104 compare an external signal IN from an input terminal 102 with their respective compare reference voltages VREF1 and VREF2.
Combinational circuit 105 outputs identify signals OUT1 and OUT2 based on the outputs from comparators 103 and 104.
Compare reference voltage VREF1 is lower than compare reference voltage VREF2. If the voltage of external signal IN is lower than compare reference voltage VREF1, then identify signal OUT1 attains a high level while identify signal OUT2 attains a low level. If the voltage of external signal IN is at a level between compare reference voltage VREF 1 and compare reference voltage VREF 2, then identify signal OUT1 attains a low level while identify signal OUT2 attains a high level. If the voltage of external signal IN is higher than compare reference voltage VREF2, then identify signal OUT1 attains a low level while identify signal OUT2 attains a low level. With such a configuration, input circuit 101 can identify three states, i.e., high, intermediate and low levels of external signal IN.
Patent Document 1: Japanese Patent Laying-Open No. 6-104664